Location: Campinas, SP, Brazil
Duration: three months, possibly to become permanent
Job hours: full-time

Responsibilities:
- Implementation and verification (RTL to GDS2) of a 65-nm digital IC for consumer applications
- Lead a small team to implement this IC
- Coordinate with Silicon Valley headquarters to plan the appropriate methodologies
- Methodology optimization and script development
- Train customer engineers in the methodologies used
- Communicate with customer front-end engineering to ensure proper alignment at all times
- Conduct design reviews
- Execute the project within budget and within schedule

Requirements:
- Must have done multiple commercial tapeouts of ICs that have gone into volume production
- Experience with Cadence-based SoC Encounter design flows
- Experience with DFT in the context of SoC Design
- Broad experience, including synthesis, floorplanning, DFT architecture and implementation, power grid planning, place and route, timing analysis, timing and SI aware routing, equivalence checking, physical verification, SI verification, and chip finishing
- Good communication and interpersonal skills
- Dedicated, hard working, team player