IP Cells
Perceptia has developed the DeepSub™ architecture for PLLs, SerDes, and Timing cells for deep submicron IC designs. The DeepSub™ technology is aimed at semiconductor processes of 65-nm and smaller, where conventional timing architectures have many challenges. DeepSub™ addresses those, and offers benefits including easy migration from one process to another and from one process node to another; smaller die area and lower power consumption. Timing performance is maintained over the full operating temperature and voltage range. DeepSub™ uniquely optimizes the mix of analog circuits and DSP, in order to consume very low power, and provide unsurpassed performance and flexibility.
We offer the following IP:
pPLL01 — 11-GHz 0.4-ps 40-nm DSP-based PLL hard IP
Some saliant specifications: Lock-in range 9-11 GHz (also available in other speed grades) Jitter <400-fs (!!!) phase noise -116dBc/Hz measured at 1-MHz offset, 10-GHz Lock-in time < 1 microsecond Dissipation 15 - 20-mW Footprint 400 by 500 microns Test silicon in 40-nm CMOS
Contact us to obtain the product brief and further info.